Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits.

Sam Kavusi, Kunal Ghosh, Abbas El Gamal

 1-23

Oversampled Time Estimation Techniques for Precision Photonic Detectors.

Robert K. Henderson, Bruce Rae, David R. Renshaw, Edoardo Charbon

 25-35

Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices.

Carlotta Guiducci, Claudio Stagni, M. Brocchi, Massimo Lanzoni, Bruno Riccò, A. Nascetti, Davide Caputo, A. De Cesare

 37-53

Electronic Detection of DNA Adsorption and Hybridization.

Ulrich Bockelmann

 55-67

Probabilistic amp; Statistical Design - the Wave of the Future.

Shekhar Borkar

 69-79

A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs.

Shan Jiang, Manh Anh Do, Kiat Seng Yeo

 81-99

Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design.

Lakshmi N. Chakrapani, Jason George, Bo Marr, Bilge E. S. Akgul, Krishna V. Palem

 101-118

Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.

Antonis Papanikolaou, Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene

 119-141

Soft Error Resilient System Design through Error Correction.

Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim

 143-156

Library Compatible Variational Delay Computation.

Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira

 157-176

A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures.

Giovanni Beltrame, Donatella Sciuto, Cristina Silvano

 177-196

Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots.

Jeff Brateman, Changjiu Xian, Yung-Hsiang Lu

 197-216

Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.

Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz

 217-240

Logic Synthesis of EXOR Projected Sum of Products.

Anna Bernasconi, Valentina Ciriani, Roberto Cordone

 241-257

A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits.

Renato Fernandes Hentschke, Sandro Sawicki, Marcelo de Oliveira Johann, Ricardo Reis

 259-279

CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization.

Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu

 281-300

Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

 301-316

Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies.

Arno Moonen, Chris Bartels, Marco Bekooij, René van den Berg, Harpreet Bhullar, Kees Goossens, Patrick Groeneveld, Jos Huisken, Jef L. van Meerbergen

 317-336

Designing Routing and Message-Dependent Deadlock Free Networks on Chips.

Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo

 337-355

Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model.

Ittetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai

 357-376

Human++: Emerging Technology for Body Area Networks.

Julien Penders, Bert Gyselinckx, Ruud J. M. Vullers, Olivier Rousseaux, Mladen Berekovic, Michael De Nil, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov

 377-397