VLSI-SoC 2003: Darmstadt, Germany
VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany
Manfred Glesner, Ricardo Augusto da Luz Reis, Leandro Soares Indrusiak, Vincent John Mooney III, Hans Eveking
Springer, IFIP 200, ISBN: 978-0-387-33402-8
Contents
Effect of Power Optimizations on Soft Error Rate.
Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
1-20
Dynamic Models for Substrate Coupling in Mixed-Mode Systems.
João M. S. Silva, Luis Miguel Silveira
21-37
Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs.
Thomas Hollstein, Ralf Ludewig, Heiko Zimmer, Christoph Mager, Simon Hohenstern, Manfred Glesner
39-54
Automated Conversion of SystemC Fixed-Point Data Types.
Axel G. Braun, Djones Lettnin, Joachim Gerlach, Wolfgang Rosenstiel
55-72
Validation of Asynchronous Circuit Specifications Using IF/CADP.
Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani
85-100
On-Chip Property Verification Using Assertion Processors.
José Augusto Miranda Nacif, Claudionor Nunes Coelho, Harry Foster, Flávio Miana de Paula, Edjard Mota, Márcia Roberta Falcão Mota, Antônio Otávio Fernandes
101-117
Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems.
Jürgen Becker, Michael Hübner, Michael Ullmann
119-132
A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications.
Giuseppe Bonfini, Andrea S. Brogna, Roberto Saletti, Cristian Garbossa, Luca Colombini, Maurizio Bacci, Stefania Chicca, Franco Bigongiari
133-147
Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans.
Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner
149-164
Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures.
Alexandre M. Amory, Leandro A. Oliveira, Fernando Gehm Moraes
165-179
Optimizing SOC Test Resources Using Dual Sequences.
Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz
181-196
A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits.
Cristiano Lazzari, Cristiano Viana Domingues, José Luís Güntzel, Ricardo Reis
197-211
Low Power Java Processor for Embedded Applications.
Antonio Carlos Schneider Beck, Luigi Carro
213-228
Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes.
Stephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel
229-245
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates.
Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
247-262
Jürgen Becker, Alexander Thomas, Maik Scheer
263-279
Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths.
Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi
281-297
Stuck-At-Fault Testability of SPP Three-Level Logic Forms.
Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
299-313